Field of the Invention
This invention relates to a semiconductor device, in particular, a semiconductor device that has a plurality of memory cell arrays.
Description of the Related Art
In a semiconductor device, such as DRAM (Dynamic Random Access Memory), a memory cell array is divided into multiple regions and data input/output terminals, data buses, etc., are arranged between the divided memory cell array regions in many cases (see patent document 1).
[Patent document 1] Japanese Laid-Open Patent Publication No. 8-139287
However, some methods of assigning memory cell array regions and data buses and of laying out data buses pose various problems, such as a shift in data input/output timing between memory cell array regions, an increase in the number of necessary shield lines, and a change in data input/output timing depending on operation modes.